The phase-locked loop (PLL) is an important part of radio frequency (RF) and millimetre-wave (MW) radio transmitters, as well as in test instruments and clock generators. The PLL generates a signal whose frequency is a multiple N of a reference frequency. One important figure of merit of a PLL is its spectral purity, quantified in phase noise and spurious content. Several PLL architectures have been presented in the last decades. One of the best performing PLLs regarding phase noise is the sub-sampling PLL.
A sub-sampling PLL (SS-PLL) is a feedback system, with an input reference clock with a period T, a sampler, a forward loop function and a voltage controlled oscillator (VCO). Assuming that the wanted frequency is an integer N times the reference frequency, i.e., every N'th VCO zero-crossing will coincide with a positive reference edge. At every multiple of the reference period T, the sinusoidal output of the VCO should cross zero. A small error in the VCO frequency, leads to a voltage error. It is this error voltage that is captured by the sampler.
The output of the sampler is usually configured to control a charge-pump consisting of two current sources, one with a fixed current and one with a current that can be modulated. The current sources are simultaneously connected to the output during a short pulse. The output current of the charge-pump is normally integrated and filtered by a loop-filter and then controls the output frequency of the VCO.
If the output frequency of the VCO is slightly too low, the sampler will sample the VCO sinusoid earlier in its cycle, at a lower voltage. This increases the net output current of the charge-pump. The LPF (Low Pass Filter) output voltage is increased and the VCO frequency is increased. The opposite happens if the VCO frequency is too high. This feedback loop keeps the VCO frequency at the desired multiple of the reference frequency.
Since the sampler can capture any VCO edge, a sub-sampling PLL has a small lock range. To circumvent this, a typical SS-PLL has an additional coarse locking loop. The SS-PLL loop is accompanied by a parallel traditional PLL loop as is known from conventional solutions.
The above described SS-PLL is limited to integer-N operation. A fractional-N sub-sampling PLL (SSF-PLL) can be implemented by introducing a controllable digital-to-time converter (DTC) in the reference input path. The principle behind the SSF-PLL is to delay the positive reference edge such that it coincides with the (ideal) zero-crossings of the VCO output. When the delay is more than one VCO period the previous VCO zero-crossing is sampled instead. This leads to a saw-tooth shaped delay of the reference clock.
The delay of the DTC is set in multiples of tD. The ideal VCO zero-crossing will in most cases not coincide with this delay. This will lead to a so called quantization error on the sampled voltage. The sampled voltage will either be too low or too high.
The limited resolution of the DTC introduces a voltage error at the output of the sampler. This will introduce spectral degradation of the PLL output. Due to the deterministic, ramp-like shape of the DTC delay, the degradation will mostly be in the form of spurious tones. Increasing the resolution is therefore of utmost importance.